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                    "Over the last few months, I\u2019ve been working on improving CPython\u2019s support for\nthe RISC-V architecture, and I\u2019m thrilled to announce that RISC-V is now\nofficially supported by CPython as a tier 3\nplatform! \ud83c\udf89 \ud83d\ude80\nWhat is RISC-V?\n\nRISC-V is an open instruction set architecture (ISA). Importantly,\nunlike proprietary instruction sets (such as x86 and ARM), it is developed as an\nopen standard and can be implemented by anyone.\nIts ecosystem has grown considerably in recent years and is projected to\nquadruple by 2032. With that growth, it\u2019s increasingly important that\nPython works reliably on these platforms.\nGetting here\nThis would not have been possible without community contributions. RISC-V support\nin CPython has developed over time with people testing on real hardware,\nfixing architecture-specific issues, improving build support, reporting bugs,\nand reviewing patches. That work is what has brought the platform to the point\nwhere it could be added to PEP 11.\n\nA particularly important part of this has been having reliable, ongoing testing\non real RISC-V hardware. I\u2019d like to thank the RISE Project for their\nsupport. RISE has kindly provided several RISC-V machines for CPython,\ngiving us buildbots for testing as well as debugging architecture-specific issues.\nI\u2019d especially like to thank Ludovic Henry from the RISE Project,\nFurkan Onder, and Emma Smith, along with the many others who have\ncontributed. Additionally, I\u2019m personally grateful for the Sovereign Tech Agency,\nwhich through their amazing fellowship supported my work on this.\nWhat\u2019s next?\nWhile tier 3 support is an important milestone, there\u2019s plenty more to do.\nWe are currently investigating how to improve our testing further by bringing\nRISC-V directly into CPython\u2019s CI, again kindly supported by RISE with their\nRISE RISC-V Runners initiative. This should give contributors faster\nfeedback than the buildbots (which usually run after a patch is merged)\nand would allow us to catch RISC-V-specific problems earlier.\nIn the long term, I\u2019d also love to work towards promoting RISC-V to tier 2 support.\nThere are also opportunities to move beyond simply making CPython work on RISC-V.\nI\u2019d like to explore architecture-specific optimizations to take better advantage\nof RISC-V capabilities where doing so can improve CPython\u2019s performance.\nImportantly, we need people to use it and give us feedback. If you have access\nto RISC-V hardware, please try building and running CPython, run your workloads\nand test suites, and please let us know what breaks. Testing across\ndifferent RISC-V environments will help us make support better for everyone!\nCPython is also only one part of the Python ecosystem. Continued community work\nacross packages, compilers, tooling, and infrastructure will be important in\nmaking RISC-V an increasingly well-supported platform for Python as a whole.\nThere\u2019s a lot still to do, and I\u2019m looking forward to continuing that work!"
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